In late February 1983 Michael Jackson’s Billie Jean was about to hit #1 (where it lasted for only one week) 🙂 At the same time this ITT 4116 16kb x 1 DRAM was packaged.
Back in the late seventies ITT was a huge conglomerate. At one point the fourth largest company in the world. Their products and services ranged from telecoms, to insurance, hotels, semiconductors and much more. For semiconductors they had manufacturing plants in Germany and the UK. Their UK plant in Sidcup (an outer suburb of London) produced all of their memory chips. 16k DRAMs were produced from 1977 to ~1985 with peak demand around 82-83 when this was made. Around 1983 was when 64k DRAM started in production – at that time ITT was the largest memory producer in Europe.
Normally DRAM is way too dense to see anything in my optical microscope. However a 1983 DRAM should be large enough feature size to look at the cell details.
Die Photo and Die Marks
The ITT 4116 is made in a two poly one metal NMOS process with ~3μm minimum dimensions as you can see in this CD (Critical Dimensions) test structure. Used to monitor the process lithography and etch steps.
And from the mask numbers it looks like this was a 7 mask process.
On a DRAM, making the smallest die size is critical to achieving the most die per wafer (And hence lowest cost per die.) To optimize the area everything is laid out manually and many of the peripheral features have novel shapes and bends.
A copy of the datasheet exists and I copy it here. ITT 4116 is pin and function compatible with the Mostek MK 4116. Mostek were by a long way the market leaders in DRAM at the 16k node. They through their co-founder Bob Proebstring invented address multiplexing that reduced the pin count and was essential for 16k and larger DRAM’s. There were several manufacturers of 4116 DRAM’s copying the Mostek part functions and pins.
A DRAM cell component design is pretty straight forward as shown here. I thought it would be easy to identify and interpret the layout for this planar DRAM. As you can see even with this old 3μm process the cell is quite complex.
I really wanted to view and illustrate the basic memory cell. So I thought I would have a go at removing the metal layer. To do this I don’t really have all the chemicals needed, I don’t have (And don’t want) HF acid to remove the dielectrics. I do have some Armour Glass Etch which is basically an HF type gel which I tried. After a few applications together with some dunks in HCl (Muriatic Acid) to etch the metal I was quite pleased to get a clean view.
Even with the metal removed I spent a long time trying to figure out how the bit lines, word lines, storage capacitor and transfer transistor are configured.
Here is the same image annotated with what I think are the active area (diffusion), poly 1 and poly 2
The capacitor is easy to figure out as the overlap of poly 1 and poly 2. The bit lines and word lines are pretty clear, but the transistor is not so obvious. Even now I am not totally sure what I label as the drain end of the transistor is configured.