Intel 8080 Microprocessor

I wanted to decap an iconic Intel 8080 microprocessor. Although (low resolution) die photos can be readily found, I wanted to take a closer look myself. Launched in April 1974 the 8080 was the successor to the 8008.  It was the first Intel CPU on an NMOS process and the first in a 40 pin package.

My one is an 8080A (With max clock speed of 3.125MHz) Intel 8080Afrom week 35 1984

I initially thought the 435 date code meant 1974 week 35 (Which would have been a very early part.) But then realized the ’79 was the design revision. Intel did a design revision in 1979 and were clearly still in production in 1984, ten years after the launch.

The 8080 was designed by Frederico Faggin along with Stan Mazor. One backstory that I find fascinating is that Faggin not only designed this (And the 4004.) He was also the inventor of the Self-Aligned Silicon gate process – one of the most important process steps that was used in every CMOS chip for the next 30 years. Even by the 1980’s the idea of a process engineer also designing chips was unthinkable, the two engineering disciplines are just too separate. Faggin left Intel to found Zilog in Nov 1974 (And designed the hugely successful Z80 CPU) and founded and was CEO/Chairman of Synaptics for many years a company making touchpad interfaces who are still around today.

Die Photo

The 8080A was 4.28mm x 4.18mm (17.9mm2) a small area die by modern day examples.Intel 8080A die photoclick on image for high resolution version

Made on a 6μm enhancement transistor NMOS process. The layout (All done manually) has dense packing of both metal and polysilicon layers. Here the polysilicon is being used as routing as the data fans out from the ROM

As well as the main die marking







There are two other die markings “mel” and “i/IL”

The “mel” marking is intringuing.  The ‘el’ are styled the same as the Intel logo, which suggest to me that this is not a designer initial.  

Datasheet and Pin Out

The datasheet was easy to find.  From this I was able to identify the pin out, and some of the key feature blocks

One of the big changes from the 8008 was the 16 bit address register array (Or stack pointer) that enabled the part to address 64kB of memory (Through the 16 Address Array input pads down the right side of the die).  The instruction register has two blocks of ROM each containing 324 bits by my count.  The bi-directional 8 bit data pins are on the top right.

Polysilicon Die Photo

With the dense metal not all features can clearly seen. Whilst 8080 die photos are not hard to find, I have never seen a polysilicon layer die photo of an 8080 anywhere.  So using a paste of Armour etch (HF based) and water to remove the dielectrics, and HCl (Muriatic acid) to etch the Aluminum I created a polysilicon die photo.

I am well pleased with the result!Intel 8080A poly die photoclick on image for high resolution version

Here is a crop from the image where I have marked up the layers to explain what you can seeI may have over-etched the oxides a bit (using homemade pastes and only having one sample it is a bit hit or miss). But you can clearly see all the transistor gates, and the source/drain regions (Active area) and even all the contacts.

This image (Plus metal die photo) would be sufficient to fully reverse engineer the chip with several hours of effort tracing the circuit.  Of course in the 1970’s the 8080 was reverse engineered by dozens of companies (Including Soviet, Polish and Czechoslovakia companies). Many second sources were made by AMD, TI, NEC, Siemens amongst others as cited in the wiki article. Back in 1970 the same microscope and etching was available, but of course there was no digital cameras.  To create a stitched image like this would have required physically taping together many paper photos!


With the metal removed the layout is much more easy to view.   Here is the a portion of the  16 bit register array at metal, and poly
Only after removing the metal can you really see the rather complex layout

And here is the register area zoomed in, first with metalThen with metal removed, you can clearly see the ROM structure (where there is a contact over active area a pass transistor is created, in empty cells there is field oxide present (No transistor)

Finally there is one structure in the bottom left quadrant that I could not figure out.  It is repeated 8 times, and it looks like there are two polysilicon to active area capacitor. Again first with metaland at poly

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Motorola MC6847P Video Display Generator

Used in the TRS-80, Acorn Atom and several other home computers the MC6847P is a video display generator enabling a TV to be used to display text and graphics. The date code is week 52 1978. (YMCA by the village people have just made #1 😉 ) It’s a 40 pin package and is a very big chunk of plastic (52mm x 14mm) compared to modern chips.Motorola MC6847P

Die Photo

Die size is  4.86 mm x 5.13 mm (24.9mm2) a fairly large die for 1978.MC6847 Die Photo

click on image for higher resolution version

The die photo has a very black and white feel, with the layers under the metal very obscured. I have seen this before, here and here.  It is clearly a characteristic of the Motorola process at the time. The poly is just visible and the active area diffusions are fully obscured. Was it deliberate or just a symptom of the process tools they used for deposition? I have a theory that it might have been deliberately done to reduce reflections from poly layers and thus improve metal lithography. Only an ex-Motorola process engineer would know.


The MC6847P datasheet is easy to find, I attach a copy here.  It even has its own wikipedia entry. The MC6847P  (P was for plastic package) interfaced the MC6800 CPU to a colour or black and white NTSC television.


Only capable of rendering 256 x 192 dots,  thats only 49,152 pixels!


I extracted the pin-out from the datasheet and die photo.   Notice there 41 bonds pads with 40 pins.  There are two Vss (Ground) bond pads one on either side of the die.

The character generator ROM is easy to spot. I think the area below the ROM is the parallel to serial shift register as per this block diagram


The Motorola MC6847P was made on the same 5μm NMOS process as the MC6800 MCU.  Buoyed by my success in removing the metal in the recent ITT 41116 I thought I would also have a try here.  So I bought out the Armour Etch again together with HCl to etch the Aluminum.  Overall the result is not too bad – here is a die photo of the poly layerMC6847 poly die photo

click on image for higher resolution version

The poly lines and the active area diffusions are now clearly visible   The field oxide has not been uniformly removed with lots of residual oxide around.  If I try to remove all this oxide residue I will likely attack and lift the polysilicon lines.

Now comparing the ROM area (Both images taken with 20x objective)

You can see how the ROM is programed with active area.  The pair of vertical polysilicon lines cross an irregular grid.  The inside of the grid lines is field oxide. Where the field oxide has been removed the polysilicon is crossing active area, so a transistor is formed.

This image shows transistors in the shift register area imaged with my 80x objectiveThe tips of the polysilicon gates terminate on the field oxide islands.  You can also see the contacts to the diffusion (to make source and drain connections) and to the polysilicon.  Also in all the contacts you can see little black dots,  this is silicon that has precipitated out of the Aluminum metal during processing.  A small amount of silicon (~1%) was typically added to Aluminum to improve the electro migration resistance of the tracks.


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ITT 4116 16k DRAM

ITT 4116 16k DRAM

In late February 1983 Michael Jackson’s Billie Jean was about to hit #1 (where it lasted for only one week) 🙂  At the same time this ITT 4116 16kb x 1 DRAM was packaged.

Back in the late seventies ITT was a huge conglomerate. At one point the fourth largest company in the world. Their products and services ranged from telecoms, to insurance, hotels, semiconductors and much more. For semiconductors they had manufacturing plants in Germany and the UK.  Their UK plant in Sidcup (an outer suburb of London) produced all of their memory chips.  16k DRAMs were produced from 1977 to ~1985 with peak demand around 82-83 when this was made.  Around 1983 was when 64k DRAM started in production – at that time ITT was the largest memory producer in Europe.

Normally DRAM is way too dense to see anything in my optical microscope.  However a 1983 DRAM should be large enough feature size to look at the cell details.

Die Photo and Die Marks

With a die size is 6.1mm x  3.95 mm (24 mm2) built on a 4″ wafer they would have had ~226 candidate dies on each wafer.ITT 4116 Die PhotoClick on image for high resolution version

The die mark also has a neat piece of silicon art.  Never published before, I feel like I have discovered a long lost artwork 🙂



The ITT 4116 is made in a two poly one metal NMOS process with ~3μm minimum dimensions as you can see in this CD (Critical Dimensions) test structure.  Used to monitor the process lithography and etch steps.



And from the mask numbers it looks like this was a 7 mask process.




On a DRAM, making the smallest die size is critical to achieving the most die per wafer (And hence lowest cost per die.) To optimize the area everything is laid out manually and many of the peripheral features have novel shapes and bends.

Here are what I believe are the column decoder and sense amps at the end of the bit lines

On this process I think the bit lines are in diffusion, and the word lines are in metal.  Here are the row decoders on the end of the word lines.


A copy of the datasheet exists and I copy it here.  ITT 4116 is pin and function compatible with the Mostek MK 4116.   Mostek were by a long way the market leaders in DRAM at the 16k node. They through their co-founder Bob Proebstring invented address multiplexing that reduced the pin count and was essential for 16k and larger DRAM’s.  There were several manufacturers of 4116  DRAM’s copying the Mostek part functions and pins.

Memory Cells

Here are the DRAM cells imaged with my highest magnification objective


A DRAM cell component design is pretty straight forward as shown here.  I thought it would be easy to identify and interpret the layout for this planar DRAM. As you can see even with this old 3μm process the cell is quite complex.





I really wanted to view and illustrate the basic memory cell. So I thought I would have a go at removing the metal layer. To do this I don’t really have all the chemicals needed, I don’t have (And don’t want) HF acid to remove the dielectrics. I do have some Armour Glass Etch which is basically an HF type gel which I tried. After a few applications together with some dunks in HCl (Muriatic Acid) to etch the metal I was quite pleased to get a clean view.

DRAM Cells after metal and oxide removed

Even with the metal removed I spent a long time trying to figure out how the bit lines, word lines, storage capacitor and transfer transistor are configured.


Here is the same image annotated with what I think are the active area (diffusion), poly 1 and poly 2



The capacitor is easy to figure out as the overlap of poly 1 and poly 2.  The bit lines and word lines are pretty clear, but the transistor is not so obvious. Even now I am not totally sure what I label as the drain end of the transistor is configured.

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Texas Instruments TRF5101

The TI TRF5101 is from around 2002. Removed from a old cell phone, but I cannot recall which one?! I know it is an RF receiver probably for cellular but I could find no information about this chip. Texas Instruments are usually one of the best companies for finding datasheets and information on older devices. But not this oneTRF5101 die markIt was sitting on my workbench for ages so I figured I would just post the die photo.

3 mm x 2.92 mm (8.76 mm2)TRF5101 die photoclick on image for higher resolution version


This is a copper metal part (I think 4 layers).  Copper metal interconnect was first introduced late in 1997 (By IBM). Being an RF chip it would not normally be made on the leading edge state-of-art small geometry device. So it’s a bit surprising they designed this chip on a Copper process in 2001.

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